View CS5566-ISZ_1504447.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this produ ct without notice. copyright ? cirrus logic, inc. 2008 (all rights reserved) http://www.cirrus.com 3/25/08 cs5566 2.5 v / 5 v, 5 ksps, 24-bit ? adc features & description ? differential analog input ? on-chip buffers for high input impedance ? conversion time = 200 s ? settles in one conversion ? linearity error = 0.0005% ? signal-to-noise = 110 db ? 24 bits, no missing codes ? simple three/four-wire serial interface ? power supply configurations: - analog: +5v/gnd; io: +1.8v to +3.3v - analog: 2.5v; io : +1.8v to +3.3v ? power consumption: 20 mw @ 5 ksps general description the cs5566 is a single-channel, 24-bit analog-to-digital converter capable of 5 ksps conversion rate. the input accepts a fully differential analog input signal. on-chip buffers provide high input im pedance for both the ain in- puts and the vref+ input. this significantly reduces the drive requirements of signal sources and reduces errors due to source impedances. the cs5566 is a delta-sigma converter capable of switchi ng multiple input channels at a high rate with no loss in throughput. the adc uses a low-latency digital filter architecture. the filter is designed for fast settling and settles to full accuracy in one conver- sion. the converter's 24-bit data output is in serial form, with the serial port acting as either a master or a slave. the converter is designed to support bipolar, ground-refer- enced signals when operated from 2.5v analog supplies. the converter can operate from an analog supply of 0-5v or from 2.5v. the digital interface supports standard log- ic operating from 1.8, 2.5, or 3.3 v. ordering in formation: see ordering information on page 30. ain+ ain- cs sclk smode vref+ vref- rdy osc/clock generator conv bp/up digital control serial interface adc digital filter logic vl mclk sdo rst sleep tst dcr v1- v2- bufen v2+ v1+ cs5566 vlr vlr2 mar ?08 ds806pp1
cs5566 2 ds806pp1 3/25/08 table of contents 1. characteristics and spec ifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 analog characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 digital characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 guaranteed logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 converter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.2 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.5 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 output coding format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 3.7 typical connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.8 ain & vref sampling structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9 converter performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 3.10 digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.11 serial port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.11.1 ssc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.11.2 sec mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.12 power supplies & grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.13 using the cs5566 in multiplexing applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.14 synchronizing multiple converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4. pin descriptions 26 5. package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 6. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7. environmental, manufact uring, & handling information . . . . . . . . . . . . . . 30 8. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
cs5566 ds806pp1 3 3/25/08 list of figures figure 1. converter status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. ssc mode - read timing, cs remaining low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. ssc mode - read timing, cs falling after rdy falls . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. sec mode - continuous sclk read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. sec mode - discontinuous sclk read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. power consumption vs. conversi on rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. voltage reference circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 8. cs5566 configured using 2.5v analog supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. cs5566 configured using a single 5v analog su pply . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. cs5566 dnl plot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. spectral performance, 0 db. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 figure 12. spectral performance, -6 db . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 figure 13. spectral performance, -12 db . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 14. spectral performance, -20 db . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 15. spectral performance, -80 db . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 16. spectral performance, -120 db . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 17. spectral performance, -130 db . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 19. noise histogram (4096 samples) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 18. spectral plot of noise with shorted input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 20. digital filter response (dc to 2.5 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 list of tables table 1. output coding, two?s complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 2. output coding, offset binary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
cs5566 4 ds806pp1 3/25/08 1. characteristics and specifications ? min / max characteristics and spec ifications are guaranteed over th e specified operating conditions. ? typical characteristics and specifications are measured at nominal supply voltages and t a = 25c. ? vlr = 0 v. all voltages with respect to 0 v. analog characteristics t a = -40 to +85 c; v1+ = v2+ = +2.5 v, 5%; v1- = v2- = -2.5 v, 5%; vl -vlr = 3.3 v, 5%; vref = (vref+) - (vref -) = 4.096v; mclk = 8 mhz; smode = vl. bufen = v1+ unless otherwise stated. connected per figure 8 . bipolar mode unless otherwise stated. 1. no missing codes is guaranteed at 24 bits re solution over the specified temperature range. 2. one lsb is equivalent to (2 x vref) 2 24 or (2 x 4.096) 16,777,216 = 488 nv. 3. scales with mclk. 4. measured using an input signal of 1 v dc. parameter min typ max unit accuracy linearity error - 0.0005 - %fs differential linearity error (note 1) - 0.1 - lsb 24 positive full-scale error - 1.0 - %fs negative full-scale error - 1.0 - %fs full-scale drift (note 2) - 1 - ppm / c bipolar offset (note 2) - 500 - lsb 24 bipolar offset drift (note 2) - 1 - lsb / c noise - 9.5 - vrms dynamic performance peak harmonic or spurious noise 200 hz, -0.5 db input - -115 - db total harmonic distortion 200 hz, -0.5 db input - -110 -100 db signal-to-noise 108 110 - db s/(n + d) ratio -0.5 db input, 200 hz -60 db input, 200 hz - - 109 50 - - db db -3 db input bandwidth (note 3) - 21 - khz analog input analog input range (differential) unipolar bipolar 0 to +vref vref v v input capacitance - 10 - pf cvf current (note 4) ain buffer on (bufen = v+) ain buffer off (bufen = v-) - - 600 130 - - na a common mode rejection ratio (dc to 2 khz) -100 -110 - db
cs5566 ds806pp1 5 3/25/08 analog characteristics (continued) t a = -40 to +85 c; v1+ = v2 + = +2.5 v, 5%; v1- = v2- = -2.5 v, 5%; vl -vlr = 3.3 v, 5%; vref = (vref+) - (vref-) = 4.096v; mc lk = 8 mhz; smode = vl.; bufen = v1+ unless otherwise stated. connected per figure 8 . 5. for optimum performance, vref+ should always be less than (v+) - 0.2 volts to prevent saturation of the vref+ input buffer. 6. specification is for mclk = 8mhz and 5 ksps conversion rate. mclk frequency and conversion rate affect power consumption. see section 3.2 power consumption for more details. 7. tested with 100 mvp-p on any supply up to 2 khz. v1+ and v2+ supplies at the same voltage potential, v1- and v2- supplies at the same voltage potential. parameter min typ max unit voltage reference input voltage reference input range (vref+) ? (vref-) (note 5) 2.4 4.096 4.2 v input capacitance - 10 - pf cvf current vref+ buffer on (bufen = v+) vref+ buffer off (bufen = v-) vref- - - - 3 1 1 - - - a ma ma power supplies average dc power supply currents (note 6) i v1 i v2 i vl - - - - - - 5 0.6 0.4 ma ma ma peak dc power supply currents (note 6) i v1 i v2 i vl - - - - - - 9 1.2 280 ma ma a average power consumption normal operation buffers on (note 6) buffers off sleep (sleep = 0) - - - 20 15 6 - - - mw mw mw power supply rejection (no te 7) v1+ , v2+ supplies v1-, v2- supplies 75 75 85 85 - - db db
cs5566 6 ds806pp1 3/25/08 switching characteristics t a = -40 to +85 c; v1+ = v2+ = +2.5 v, 5%; v1- = v2- = -2.5 v, 5%; vl - vlr = 3.3 v, 5%, 2.5 v, 5%, or 1.8 v, 5% input levels: logic 0 = 0v low; logic 1 = vd+ = high; cl = 15 pf. 8. bp/up can be changed coincident conv falling. bp/up must remain stable until rdy falls. 9. if conv is held low continuously, conver sions occur every 1600 mclk cycles. if rdy is tied to conv , conversions will occur every 1602 mclks. if conv is operated asynchronously to mclk, a conversion may take up to 1604 mclks. rdy falls at the end of conversion. 10. rdy will fall when the device is fully operational when coming out of sleep mode. figure 1. converter status (not to scale) parameter symbol min typ max unit master clock frequenc y internal oscillator external clock xin f clk 6 0.5 7 8 8 8.1 mhz mhz master clock duty cycle 40 - 60 % reset rst low time t res 1- -s rst rising to rdy falling internal oscillator external clock t wup - - 240 3084 - - s mclks conversion conv pulse width t cpw 4- -mclks bp/up setup to conv falling (note 8) t scn 0- -ns conv low to start of conversion t scn - 1182 1186 mclks perform single conversion (conv high before rdy falling) t bus 20 - - mclks conversion time (note 9) start of conversion to rdy falling t buh - - 1604 mclks sleep mode sleep low to low-power state sleep high to device active (note 10) t con t con - - 50 3083 - - s mclks 1182 - 1186 mclks converter status convert rdy idle idle convert sdo active t bus 354 + 64 mclks 1600 - 1604 mclks
cs5566 ds806pp1 7 3/25/08 switching characteristics (continued) t a =-40to+85c;v1+=v2+=+2.5 v, 5%; v1- = v2- = -2.5 v, 5%; vl - vlr = 3.3 v, 5%, 2.5 v, 5%, or 1.8 v, 5% input levels: logic 0 = 0v low; logic 1 = vd+ = high; cl = 15 pf. 11. sdo and sclk will be high impedance when cs is high. in some systems it ma y require a pull-down resistor. 12. sclk = mclk/2. parameter symbol min typ max unit serial port timing in ssc mode (smode = vl) rdy falling to msb stable t 1 --2-mclks data hold time after sclk rising t 2 -10-ns serial clock (out) pulse width (low) (note 11, 12) pulse width (high) t 3 t 4 100 100 - - - - ns ns rdy rising after last sclk rising t 5 -8-mclks mclk rdy sclk(o) sdo msb msb ? 1 lsb lsb+1 cs t 1 t 2 t 3 t 4 t 5 figure 2. ssc mode - read timing, cs remaining low (not to scale)
cs5566 8 ds806pp1 3/25/08 switching characteristics (continued) t a =-40to+85c;v1+=v2+=+2.5 v, 5%; v1- = v2- = -2.5 v, 5%; vl - vlr = 3.3 v, 5%, 2.5 v, 5%, or 1.8 v, 5% input levels: logic 0 = 0v low; logic 1 = vd+ = high; cl = 15 pf. 13. sdo and sclk will be high impedance when cs is high. in some systems sclk and sdo may require pull-down resistors. 14. sclk = mclk/2. parameter symbol min typ max unit serial port timing in ssc mode (smode = vl) data hold time after sclk rising t 7 -10-ns serial clock (out) pulse width (low) (note 13, 14) pulse width (high) t 8 t 9 100 100 - - - - ns ns rdy rising after last sclk rising t 10 -8-mclks cs falling to msb stable t 11 -10-ns first sclk rising after cs falling t 12 -8-mclks cs hold time (low) after sclk rising t 13 10 - - ns sclk, sdo tri-state after cs rising t 14 -5-ns mclk rdy sclk(o) sdo cs t 12 t 8 t 13 t 9 t 7 t 11 msb msb ? 1 lsb lsb+1 t 14 t 10 figure 3. ssc mode - read timing, cs falling after rdy falls (not to scale)
cs5566 ds806pp1 9 3/25/08 switching characteristics (continued) t a =-40to+85c;v1+=v2+=+2.5 v, 5%; v1- = v2- = -2.5 v, 5%; vl - vlr = 3.3 v, 5%, 2.5 v, 5%, or 1.8 v, 5% input levels: logic 0 = 0v low; logic 1 = vd+ = high; cl = 15 pf. 15. sdo will be high impedance when cs is high. in some systems sdo ma y require a pull-down resistor. parameter symbol min typ max unit serial port timing in sec mode (smode = vlr) sclk(in) pulse width (high) - 30 - - ns sclk(in) pulse width (low) - 30 - - ns cs hold time (high) after rdy falling t 15 10 - - ns cs hold time (high) after sclk rising t 16 10 - - ns cs low to sdo out of hi-z (note 15) t 17 -10-ns data hold time after sclk rising t 18 -10-ns data setup time before sclk rising t 19 10 - - ns cs hold time (low) after sclk rising t 20 10 - ns rdy rising after sclk falling t 21 -10-ns 1 sclk 10 mclk sclk(i) sdo cs rdy lsb msb t 19 t 18 t 20 t 17 t 16 t 15 t 21 figure 4. sec mode - continuous sclk read timing (not to scale)
cs5566 10 ds806pp1 3/25/08 digital characteristics t a = tmin to tmax; vl = 3.3v, 5% or vl = 2.5v, 5% or 1.8v, 5%; vlr = 0v digital filter characteristics t a = tmin to tmax; vl = 3.3v, 5% or vl = 2.5v, 5% or 1.8v, 5%; vlr = 0v 16. see figure 4 to understand conversion timing. the 160 mclk group delay occurs during the 354 mclk high-power period of a conversion cycle. see section 3.2 power consumption for more detail. parameter symbol min typ max unit input leakage current i in --2a digital input pin capacitance c in -3-pf digital output pin capacitance c out -3-pf mclk sclk(i) sdo cs rdy lsb msb t 19 t 18 t 20 t 17 t 15 t 21 figure 5. sec mode - discontinuous sclk read timing (not to scale) parameter symbol min typ max unit group delay (note 16) - - 160 - mclks
cs5566 ds806pp1 11 3/25/08 guaranteed logic levels t a =-40to+85c;v1+=v2+=+2.5 v, 5%; v1- = v2- = -2.5 v, 5%; vl - vlr = 3.3 v, 5%, 2.5 v, 5%, or 1.8 v, 5% input levels: logic 0 = 0v low; logic 1 = vd+ = high; cl = 15 pf. guaranteed limits parameter sym vl min typ max unit conditions logic inputs minimum high-level input voltage: v ih 3.3 1.9 v 2.5 1.6 1.8 1.2 maximum low-level input voltage: v il 3.3 1.1 v 2.5 0.95 1.8 0.6 logic outputs minimum high-level output voltage: v oh 3.3 2.9 v i oh =-2ma 2.5 2.1 1.8 1.65 maximum low-level output voltage: v ol 3.3 0.36 v i oh =-2ma 2.5 0.36 1.8 0.44
cs5566 12 ds806pp1 3/25/08 recommended operating conditions (vlr = 0v, see note 17 ) 17. the logic supply can be any value vl ? vlr = +1.71 to +3.465 volts as long as vlr v2- and vl 3.465 v. 18. the differential voltage reference magnitude is constrained by the v1+ or v1- supply magnitude. absolute maximum ratings (vlr = 0v ) notes: 19. v1+ = v2+; v1- = v2- 20. v1- = v2- 21. transient currents of up to 1 00 ma will not cause scr latch-up. warning: recommended operating conditions indicate limits to which the device is functionally operational. abso- lute maximum ratings indicate limits beyond which permanent damage to the device may occur. the ab- solute maximum ratings are stress ratings only and the device should not be operated at these limits. operation at conditions beyond the recommended operat ing conditions may affect device reliability, and functional operation beyond recommended operating condit ions is not implied. performance specifica- tions are intended for the conditions specified for each table in the characteristics and specifications sec- tion. parameter symbol min typ max unit single analog supply dc power supplies: (note 17) v1+ v2+ v1- v2- v1+ v2- v1+ v2- 4.75 4.75 - - 5.0 5.0 0 0 5.25 5.25 - - v v v v dual analog supplies dc power supplies: (note 17) v1+ v2+ v1- v2- v1+ v2- v1+ v2- +2.375 +2.375 -2.375 -2.375 +2.5 +2.5 -2.5 -2.5 +2.625 +2.625 -2.625 -2.625 v v v v analog reference voltage (note 18) [vref+] ? [vref-] vref 2.4 4.096 4.2 v parameter symbol min typ max unit dc power supplies: [v1+] ? [v1-] (note 19) vl + [ |v1-| ] (note 20) - - 0 0 - - 5.5 6.1 v v input current, any pin ex cept supplies (note 21) i in --10ma analog input voltage (ain and vref pins) v ina (v1-) ? 0.3 - (v1+) + 0.3 v digital input voltage v ind vlr ? 0.3 - vl + 0.3 v storage temperature t stg -65 - 150 c
cs5566 ds806pp1 13 3/25/08 2. overview the cs5566 is a 24-bit analog-to-digital converter ca pable of 5 ksps conversion rate. the device is ca- pable of switching multiple input channels at a high rate with no loss in throughput. the adc uses a low-latency digital filter architecture. the filter is des igned for fast settling and settles to full accuracy in one conversion. the converter is a serial output device. the serial po rt can be configured to function as either a master or a slave. the converter can operate from an analog supply of 5v or from 2.5v. the digital interface supports stan- dard logic operating from 1.8, 2.5, or 3.3 v. the cs5566 converts at 5 ksps when operating from a 8 mhz input clock. 3. theory of operation the cs5566 converter provides high-performance meas urement of dc or ac signals. the converter can be used to perform single conversi ons or continuous conversions upon command. each conversion is in- dependent of previous conversions and can settle to fu ll specified accuracy, even with a full-scale input voltage step. this is due to the converter architecture which uses a combination of a high-speed delta-sig- ma modulator and a low-latency filter architecture. once power is established to the converter, a reset must be performed. a reset initializes the internal con- verter logic. if conv is held low then the converter will convert continuously with rdy falling every 1600 mclks. this is equivalent to 5 ksps if mclk = 8.0 mhz. if conv is tied to rdy , a conversion will occur every 1602 mclks. if conv is operated asynchronously to mclk, it may take up to 1604 mclks from conv falling to rdy falling. multiple converters can operate synchronously if they are driven by the same mclk source and conv to each converter falls on the same mclk falling edge. alternately, conv can be held low and all devices are reset with rst rising on the same falling edge of mclk. the output coding of the conversion word is a function of the bp/up pin. the active-low sleep signal causes the device to enter a low-power state. when exiting sleep, the con- verter will take 3083 mclk cycles before conversions can be performed. rst should remain inactive (high) when sleep is asserted (low).
cs5566 14 ds806pp1 3/25/08 3.1 converter operation the converter should be reset after the power supplies and voltage reference are stable. the cs5566 converts at 5 ksps when synchronously operated (conv = vlr) from a 8.0 mhz master clock. conversion is initiated by taking conv low. a conversion lasts 1600 master clock cycles, but if conv is asynchronous to mclk there may be an unc ertainty of 0-4 mclk cycles after conv falls to when a conversion actually begins. this may extend the throughput to 1604 mclks when the conversion is completed, the output word is placed into the serial port and rdy goes low. to convert continuously, conv should be held low. in conti nuous conversion mode with conv held low, a conversion is performed in 1600 mclk cycles. alternately rdy can be tied to conv and a conversion will occur every 1602 mclk cycles. to perform only one conversion, conv should return high at least 20 master clock cycles before rdy falls. once a conversion is completed and rdy falls, rdy will return high when all the bits of the data word are emptied from the serial port or if the conversion data is not read and cs is held low, rdy will go high two mclk cycles before the end of conversion. rdy will fall at the end of the next conversion when new data is put into the port register. see section 3.11 serial port for information about reading conversion data. conversion performance can be affected by several fact ors. these include the choice of clock source for the chip, the timing of conv , and the choice of the serial port mode. the converter can be operated from an internal oscill ator. this clock source has greater jitter than an ex- ternal crystal-based clock. jitter may not be an issu e when measuring dc signals, or very-low-frequency ac signals, but can become an issue for higher frequency ac signals. for maximum performance when digitizing ac signals, a low- jitter mclk should be used. to maximize performance, the conv pin should be held low in the co ntinuous conversion state to per- form multiple conversions, or conv should occur synchronous to mclk , falling when mclk falls. if the converter is operated at maximum throughput, the ssc serial port mode is less likely to cause in- terference to measurements as the sclk output is synchronized to the mclk. alternately, any interfer- ence due to serial port clocking can also be minimize d if data is read in the sec serial port mode when a conversion is not in progress.
cs5566 ds806pp1 15 3/25/08 3.2 power consumption the power consumption of the cs5566 converte r is a function of the conversion rate. figure 6 illustrates the typical power consumption of the converter when operating from either mclk = 8 mhz or mclk = 4 mhz. the rate at which conversions are performed directly affects the power consumption. when the converter is powered but not converting, it is in an idle state where its power consumption is about 11 mw. when the conv signal goes low to start a conversion, the converter delays the actual start of conversion for 1182 to 1186 mc lk cycles, depending upon how conv is controlled. the timing for the conversion sequence is shown in figure 1 on page 6. after the 1182 - 1186 mclk delay from when conv goes low, the converter enters a higher-power st ate for 354 mclk cycles and then returns to a lower-power state for 64 mclk cycles, after which the rdy signal falls to indicate the completion of a conversion. since the peak operating current for the converter occurs during the 354 mclk, higher-pow- er state, it is recommended that a large capacitor be used on the supply to the converter (as shown in figures 9 and 10). this capacitor filters the peak cu rrent demand from the power supply. the average power consumption for the converter will depend upon the frequency of mclk and the rate at which con- versions are performed as illustrated in figure 1 on page 6. figure 6. power consumption vs. conversion rate 7.5 10 12.5 15 17.5 20 0 5001k 1.5 2k2.5k3k3.5k4k4.5k5k word rate (sps) power consumption (mw) mclk = 8mhz mclk = 4mhz
cs5566 16 ds806pp1 3/25/08 3.3 clock the cs5566 can be operated from its internal oscillator or from an external master clock. the state of mclk determines which clock source will be used. if mclk is tied low, the internal oscillator will start and be used as the clock source for the converter. if an external cmos-compatible clock is input into mclk the converter will power down the internal oscillator and use the external clock. if the mclk pin is held high, the internal oscillator will be held in the stopped state. the mclk input can be held high to delete clock cycles to aid in operating multiple converters in different phase relationships. the internal oscillator can be used if the signals to be measured are essentially dc. the internal oscillator exhibits jitter at about 500 picoseconds rms. if the cs 5566 is used to digitize ac signals, an external low-jitter clock source should be used. if the internal oscillator is used as the clock for t he cs5566, the maximum conversion rate will be dictated by the oscillator frequency. if driven from an external mclk source, the fast rise and fall times of the mclk signal can result in clock coupling from the internal bond wire of the ic to the analog input. adding a 50 ohm resistor on the external mclk source significantly reduces this effect. 3.4 voltage reference the voltage reference for the cs5566 can range from 2.4 volts to 4.2 volts. a 4.096 volt reference is re- quired to achieve the specified performance. figure 8 and figure 9 illustrate the connection of the voltage reference with either a single +5 v analog supply or with 2.5 v. for optimum performance, the voltage reference device should be one that provides a capacitor connec- tion to provide a means of noise filt ering, or the output should include so me type of bandwidth-limiting fil- ter. some 4.096 volt reference devices need only 5 volts total supply for operation and can be connected as shown in figure 8 or figure 9 . the reference should have a local bypass capacitor and an appropriate output capacitor. some older 4.096 voltage reference designs require more headroom and must operate from an input volt- age of 5.5 to 6.5 volts. if this type of voltage reference is used ensure that when power is applied to the system, the voltage reference rise time is slower than the rise time of the v1+ and v1- power supply volt- age to the converter. an example circuit to slow the output startup time of the reference is illustrated in figure 7 . figure 7. voltage reference circuit 2k 10 f 5.5 to 15 v vin vout gnd 4.096 v refer to v1- and vref1 pins.
cs5566 ds806pp1 17 3/25/08 3.5 analog input the analog input of the converter is fully differential with a peak-to-peak input of 4.096 volts on each input. therefore, the differential, peak-to-peak input is 8.192 volts. this is illustrated in figure 8 and figure 9 . these diagrams also illustrate a differential buffer amplifier configuration for driving the cs5566. the capacitors at the outputs of the amplifiers provide a charge reservoir for the dynamic current from the a/d inputs while the resistors isolate the dynamic curre nt from the amplifier. the amplifiers can be pow- ered from higher supplies than those used by the a/d but precautions should be taken to ensure that the opamp output voltage remains within the power supply limits of the a/d, especially under start-up condi- tions. 3.6 output coding format the reference voltage directly defines the input voltage range in both the unipolar and bipolar configura- tions. in the unipolar configuration (bp/up low), the first code transition oc curs 0.5 lsb above zero, and the final code transition occurs 1.5 lsbs below vref. in the bipolar configuration (bp/up high), the first code transition occurs 0.5 lsb above -vref and the last transition occurs 1.5 lsbs below +vref. see table 1 for the output coding of the converter. note: vref = (vref+) - (vref-) table 1. output coding, two?s complement bipolar input voltage two?s complement >(vref-1.5 lsb) 7f ff ff vref-1.5 lsb 7f ff ff 7f ff fe -0.5 lsb 00 00 00 ff ff ff -vref+0.5 lsb 80 00 01 80 00 00 <(-vref+0.5 lsb) 80 00 00 note: vref = (vref+) - (vref-) table 2. output c oding, offset binary unipolar input voltage offset binary >(vref-1.5 lsb) ff ff ff vref-1.5 lsb ff ff ff ff ff fe (vref/2)-0.5 lsb 80 00 00 7f ff ff +0.5 lsb 00 00 01 00 00 00 <(+0.5 lsb) 00 00 00
cs5566 18 ds806pp1 3/25/08 3.7 typical connection diagrams the following figure depicts the cs5566 powered from bipolar analog supplies, +2.5 v and - 2.5 v. figure 8. cs5566 configured using 2.5v analog supplies vref- vref+ +4.096 voltage reference (note 1) +2.5 v smode cs 5 sclk 5 sdo rdy conv mclk sleep rst bp/up 1. see section 3.3 voltage reference for information on required voltage reference performance criteria. 2.locate capacitors so as to minimize loop length. 3. the 2.5 v supplies should also be bypassed to ground at the converter. 4. vlr and the power supply ground for the 2.5 v should be connected to the same ground plane under the chip. 5. sclk and sdo may require pull-down resistors in some applications. 6. an rc input filter can be used to band limit the input to reduce noise. select r to be equal to the parallel combination of the feedback of the feedback resistors 4.99k || 4.99k = 2.5k 00 notes -2.5 v bufen (v-) buffers off (v+) buffers on 10 f0.1 f v1+ v2+ v1- v2- vl vlr dcr +2.5 v +3.3 v to +1.8 v 0.1 f 0.1 f x7r 0.1 f 10 -2.5 v cs5566 tst 10 0.1 f ain- ain+ 49.9 47pf 4.99k 4700pf c0g 49.9 47pf 4.99k 4700pf c0g 4.99k 4.99k -2.048 v +2.048 v 0 v +2.048 v -2.048 v 0 v r 1 r 1 c 1 c 1 50 vlr2 47 f
cs5566 ds806pp1 19 3/25/08 the following figure depicts the cs5566 devic e powered from a single 5v analog supply. figure 9. cs5566 configured using a single 5v analog supply ain- ain+ smode cs 4 sclk 4 sdo rdy conv bp/up mclk sleep rst tst vref- vref+ +4.096 voltage reference (note 1) +5 v bufen 1. see section 3.3 voltage reference for information on required voltage reference performance criteria. 2. locate capacitors so as to minimize loop length. 3. v1-, v2-, and vlr should be connected to the same ground plane under the chip. 4. sclk and sdo may require pull-down resistors in some applications. notes 0.1 f (v-) buffers off (v+) buffers on 0.1 f 10 f v1+ v2+ v1- v2- vl vlr dcr +5 v +3.3 v to 1.8 v 0.1 f 0.1 f x7r 0.1 f 10 cs5566 49.9 47pf 4.99k 4700pf c0g 49.9 47pf 4.99k 4700pf c0g +0.452 v 4.548 v 2.5 v +4.548 v +0.452 v 2.5 v 2.048 v 4.096 v 50 vlr2 47 f
cs5566 20 ds806pp1 3/25/08 3.8 ain & vref sampling structures the cs5566 uses on-chip buffers on the ain+, ain-, and the vref+ inputs. buffers provide much higher input impedance and therefore reduce the amount of driv e current required from an external source. this helps minimize errors. the buffer enable (bufen) pin determines if the on-chip buffers are used or not. if the bufen pin is con- nected to the v1+ supply, the buffers will be enabled. if the bufen pin is connected to the v1- pin, the buffers are off. the converter will consume about 5 mw less power when the buffers are off, but the input impedances of ain+, ain- and vref+ will be significantly less than with the buffers enabled. 3.9 converter performance the cs5566 achieves excellent differential nonlinearity (dnl). figure 10 illustrates the code widths on the typical scale of 1 lsb and on a zoomed scale of 0.2 lsb. figure 10. cs5566 dnl plot (zoom view)
cs5566 ds806pp1 21 3/25/08 figure 11 through figure 16 illustrate the performance of the converter with various input signal magni- tudes. -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 500 1k 1.5k 2k 2.5k frequency (hz) 277 hz, 0 db 32k samples @ 5 ksps -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 500 1k 1.5k 2k 2.5k frequency (hz) 277 hz, -6 db 32k samples @ 5 ksps -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 500 1k 1.5k 2k 2.5k frequency (hz) 277 hz, -12 db 32k samples @ 5 ksps -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 500 1k 1.5k 2k 2.5k frequency (hz) 277 hz, -20 db 32k samples @ 5 ksps -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 500 1k 1.5k 2k 2.5k frequency (hz) 277 hz, -80 db 32k samples @ 5 ksps -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 500 1k 1.5k 2k 2.5k frequency (hz) 277 hz, -120 db 32k samples @ 5 ksps figure 11. spectral performance, 0 db figure 12. spectral performance, -6 db figure 13. spectral performance, -12 db figure 14. spectral performance, -20 db figure 15. spectral performance, -80 db figure 16. spectral performance, -120 db
cs5566 22 ds806pp1 3/25/08 figure 16 illustrates the device with a small signal 1/1, 000,000 of full scale. the signal input for figure 15 is about 8.2 microvolts peak to peak , or about 17 codes peak to peak. figure 17 illustrates the converter with a signal at about 2.6 microvolts peak to peak , or about 5 codes peak to peak. the cs5566 achieves superb performance with this small signal. figure 18 illustrates the noise floor of th e converter from 0.1 hz to 2.5 khz. the plot is entirely free of spu- rious frequency content due to digi tal activity inside the chip. figure 19 illustrates a noise histogram of the c onverter constructed from 4096 samples. -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 500 1k 1.5k 2k 2.5k frequency (hz) 277 hz, -130 db 32k samples @ 5 ksps 0 10 20 30 40 50 60 70 80 90 100 4096 samples mean = 96.32 std. dev. = 21.3 max - min = 150 output codes number of occurances -180 -160 -140 -120 -100 -80 -60 0.1 1 10 100 1k 2.5k frequency (hz) shorted input 2m samples @ 5 ksps 16 averages figure 17. spectral performance, -130 db figure 19. noise histogram (4096 samples) figure 18. spectral plot of noise with shorted input
cs5566 ds806pp1 23 3/25/08 3.10 digital filt er characteristics the digital filter is designed for fast settling, therefor e it exhibits very little in-band attenuation. the filter attenuation is -0.0414 db at 2.5 khz when sampling at 5 ksps. figure 20. digital filter response (dc to 2.5 khz) frequency (hz) -0.001646 db -0.00663 db -0.0149 db -0.0262 db -0.0414 db fs = 5 ksps
cs5566 24 ds806pp1 3/25/08 3.11 serial port the serial port on the cs5566 can operate in two different modes: synchronous self clock (ssc) mode & synchronous external clock (sec) mode. the serial por t must be placed into the sec mode if the offset and gain registers of the converter are to be read or written. the converter must be idle when reading or writing to the on-chip registers. 3.11.1 ssc mode if the smode pin is high (smode = vl), the serial port operates in the ssc (synchronous self clock) mode. in the ssc mode the port shi fts out conversion data words with sclk as an output. sclk is gen- erated inside the converter from mclk. data is output from the sdo (serial data output) pin. if cs is high, the sdo and sclk pins will stay in a high-impedance state. if cs is low when rdy falls, the con- version data word will be output from sdo msb first. da ta is output on the rising edge of sclk and should be latched into the external logic on the subsequent rising edge of sclk. when all bits of the conversion word are output from the port the rdy signal will return to high. 3.11.2 sec mode if the smode pin is low (smode = vlr), the serial port operates in the sec (synchronous external clock mode). in this mode, the user usually monitors rdy . when rdy falls at the end of a conversion, the conversion data word is placed into the output data register in the serial port. cs is then activated low to enable data output. note that cs can be held low continuously if it is not necessary to have the sdo output operate in the high impedance state. when cs is taken low (after rdy falls) the conversion data word is then shifted out of the sdo pin by driving the sclk pin from system logic external to the converter. data bits are advanced on rising edges of sclk and latched by the subsequent rising edge of sclk. if cs is held low continuously, the rdy signal will fall at the end of a conversion and the conversion data will be placed into the serial port. if the user starts a read, the user will maintain control over the serial port until the port is empty. however, if sclk is not toggled, the converter will overwrite the conversion data at the completion of the next conversion. if cs is held low and no read is performed, rdy will rise just prior to the end of the next conversion and then fall to signal that new data has been written into the serial port.
cs5566 ds806pp1 25 3/25/08 3.12 power supplies & grounding the cs5566 can be configured to operate with its anal og supply operating from 5v, or with its analog sup- plies operating from 2.5v. the digital interface supports digital logic operating from either 1.8v, 2.5v, or 3.3v. figure 8 on page 18 illustrates the device configured to operate from 2.5v analog. figure 9 on page 19 illustrates the device configured to operate from 5v analog. note that the schematic indicates a 47 f ca- pacitor between v1+ and v1-. this capacitor is necessary to reduce the peak current required from the power supply during conversion. see power consumption on page 16 for a more detailed discussion. to maximize converter performance, the analog groun d and the logic ground for the converter should be connected at the converter. in the dual analog supply configuration, the analog ground for the 2.5v sup- plies should be connected to the vlr pin at the conver ter with the converter placed entirely over the an- alog ground plane. in the single analog supply configuration (+5v), the ground for the +5v supply should be directly tied to the vlr pin of the converter with the converter pl aced entirely over the analog ground plane. refer to figure 9 on page 19. 3.13 using the cs5566 in mu ltiplexing applications the actual conversion process inside the cs 5566 begins 1182 mclk cycles after the conv signal is tak- en low. this would be over 147 microseconds when mc lk = 8 mhz. if the input channel of an external multiplexer is changed coincident with conv going low, the 1182 mclk delay should be more than an adequate time for settling. if there is an operational amplifier between the multiplexer and the converter, one should be certain that the amplifier can settle within the 1182 mclk delay period. if not, the multiplex- er will need to be switched some time prior to conv going low. 3.14 synchronizing multiple converters many measurement systems have multiple converte rs that need to operate synchronously. the convert- ers should all be driven from the same master clock. in this configuration, the converters will convert syn- chronously if the same conv signal is used to drive all the converters, and conv falls on a falling edge of mclk. if conv is held low continuously, reset (rst ) can be used to synchronize multiple converters if rst is released on a falling edge of mclk.
cs5566 26 ds806pp1 3/26/08 4. pin descriptions cs ? chip select, pin 1 the chip select pin allows an external devic e to access the serial port. if smode = vl (ssc mode) and cs is held high, the sdo output a nd the sclk output will be held in a high-impedance output state. tst ? factory test, pin 2 factory test only. connect to vlr. smode ? serial m ode select, pin 3 the serial interface mode pin (smode) dictates wh ether the serial port behaves as a master or slave interface. if smode is tied high (to vl ), the port will operat e in the synchronous self-clocking (ssc) mode. in ssc mode, the port ac ts as a master in which the converter out- puts both the sdo and sclk signals. if smode is tied low (to vlr), the port will operate in the synchronous external clocking (sec) mode. in se c mode, the port acts as a slave in which the external logic or microcontroller generates the sclk used to output the conversion data word from the sdo pin. ain+, ain- ? differential analog input, pin 4, 5 ain+ and ain- are differential inputs for the converter. v1- ? negative power 1, pin 6 the v1- and v2- pins provide a negative supply vo ltage to the core circuitry of the chip. these two pins should be decoupled as shown in t he application block diagrams. v1- and v2- should be supplied from the same source voltage. for si ngle-supply operation, these two voltages are nominally 0 v (ground). for dual-supply operation, they are nominally -2.5 v. v1+ ? positive power 1, pin 7 the v1+ and v2+ pins provide a positive supply vo ltage to the core circui try of the chip. these two pins should be decoupled as shown in the application block diagrams. v1+ and v2+ should be supplied from the same source voltage. for si ngle supply-operation, these two voltages are nominally +5 v. for dual-supply oper ation, they are nominally +2.5 v. bufen ? buffer enable, pin 8 buffers on input pins ain+ and ain- are enabled if bufen is connected to v1+ and disabled if connected to v1-. vref+, vref- ? voltage reference input, pin 9, 10 a differential voltage reference input on these pins functions as the vo ltage reference for the converter. the voltage between these pins can range between 2.4 volts and 4.2 volts, with 4.096 volts being the nominal reference voltage value. sleep 12 sleep mode select bp/up 11 bipolar/unipolar select vref- 10 voltage reference input vref+ 9 voltage reference input bufen 8 buffer enable v1+ 7 positive power 1 v1- 6 negative power 1 ain- 5 differential analog input ain+ 4 differential analog input 3 2 cs 1 chip select rst 13 reset vlr2 14 logic interface return conv 15 convert dcr 16 digital core regulator v2+ 17 positive voltage 2 v2- 18 negative voltage 2 mclk 19 master clock vlr 20 logic interface return vl 21 logic interface power sdo 22 serial data output sclk 23 serial clock input/output rdy 24 ready tst factory test smode serial mode select
cs5566 ds806pp1 27 3/25/08 bp/up ? bipolar/unipolar select, pin 11 the bp/up pin determines the span and the output c oding of the converter. when set high to select bp (bipolar), the input span of the converter is -4.096 volts to +4.096 volts fully differential (assuming the voltage reference is 4.096 volts) an d output data is coded in two's complement format. when set low to select up (unipolar), the input span is 0 to +4.096 fully differential and the output data is coded in binary format. sleep ? sleep mode select, pin 12 when taken low, the sleep pin will cause the conv erter to enter into a low-power state. sleep will stop the internal osc illator and powe r down all internal analog circuitry. rst ? reset, pin 13 reset is necessary after powe r is initially applied to th e converter. when the rst input is taken low, the logic in the converter will be reset. when rst is released to go high, certain portions of the analog circuitry are started. rdy falls when rese t is complete. conv ? convert, pin 15 the conv pin initiates a conversion cycle if taken low, unless a previous conversion is in progress. when the conversion cycle is completed, the conversion word is output to the serial port register and the rdy signal goes low. if conv is held low and remains low when rdy falls, another conversion cycle will be started. dcr ? digital core regulator, pin 16 dcr is the output of the on-chip regulator for the digital logic core. dcr should be bypassed with a capacitor to v2-. the dcr pin is not designed to power any external load. v2+ ? positive power 2, pin 17 the v1+ and v2+ pins provide a positive supply voltage to the circuitry of the chip. these two pins should be decoupled as shown in the application block diagrams. v1+ and v2+ should be supplied from the same source voltage. for si ngle-supply operation, these two voltages are nominally +5 v. for dual-supply oper ation, they are nominally +2.5 v. v2- ? negative power 2, pin 18 the v1- and v2- pins provide a negative supply vo ltage to the circuitry of the chip. these two pins should be decoupled as shown in the app lication block diagrams. v1- and v2- should be supplied from the same source voltage. for si ngle-supply operation, these two voltages are nominally 0 v (ground). for dual-supply operation, they are nominally -2.5 v. mclk ? master clock, pin 19 the master clock pin (mclk) is a multi-function pin. if tied low (mclk = vlr), the on-chip oscil- lator will be enabled. if tied high (mclk = vl), a ll clocks to the internal ci rcuitry of th e converter will stop. when mclk is held hi gh the internal oscillator will al so be stopped. mclk can also function as the input for an external cmos-compa tible clock that conforms to supply voltages on the vl and vlr pins. vlr2, vlr, vl ? logic interface power/return, pins 14, 20, 21 vl and vlr are the supply voltages for the digital logic interface. vl and vlr can be config- ured with a wide range of common mode voltage. the following interface pins function from the vl/vlr supply: smode, cs , sclk, sdo, rdy , sleep , conv , rst , bp/up , and mclk. sdo ? serial data output, pin 22 sdo is the output pin for the seri al output port. data from this pin will be output at a rate deter- mined by sclk and in a format determined by the bp/up pin. data is output msb first and advances to the next data bit on the rising edges of sclk. sdo will be in a high impedance state when cs is high.
cs5566 28 ds806pp1 3/25/08 sclk ? serial clock input/output, pin 23 the smode pin determines whether the sclk signal is an input or an output signal. sclk determines the rate at which data is clocked ou t of the sdo pin. if the converter is in ssc mode, the sclk frequency will be determined by the master clo ck frequency of the converter (either mclk or the internal os cillator). in sec mode, the user determin es the sclk frequency. if smode = vl (ssc mode), sclk will be in a high-imped ance state when cs is high. rdy ? ready, pin 24 if conv is low the converter will immedi ately start a conversion and rdy will remain high until the conversion is completed. at the end of any conversion rdy falls to indicate that a conver- sion word has been placed into the serial port. rdy will return high after a ll data bits are shifted out of the serial port or two master clock cycles before new data becomes available if the cs pin is inactive (high); or two mast er clock cycles before new data becomes available if the user holds cs low but has not started reading the data from the converter when in sec mode.
cs5566 ds806pp1 29 3/25/08 5. package dimensions notes: 1.?d? and ?e1? are reference datums and do not included mold flas h or protrusions, but do include mold mismatch and are measure d at the parting line, mold flash or prot rusions shall not exceed 0.20 mm per side. 2.dimension ?b? does not include dambar prot rusion/intrusion. allowable dambar protru sion shall be 0.13 mm total in excess of ?b ? dimension at maximum material condition. dambar intrusion shall not reduce dimens ion ?b? by more than 0.07 mm at least material condition. 3.these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.084 -- -- 2.13 a1 0.002 0.006 0.010 0.05 0.13 0.25 a2 0.064 0.068 0.074 1.62 1.73 1.88 b 0.009 -- 0.015 0.22 -- 0.38 2,3 d 0.311 0.323 0.335 7.90 8.20 8.50 1 e 0.291 0.307 0.323 7.40 7.80 8.20 e1 0.197 0.209 0.220 5.00 5.30 5.60 1 e 0.022 0.026 0.030 0.55 0.65 0.75 l 0.025 0.03 0.041 0.63 0.75 1.03 0 4 8 0 4 8 jedec #: mo-150 controlling dimension is millimeters. 24l ssop package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
cs5566 30 ds806pp1 3/25/08 6. ordering information 7. environmental, manufact uring, & handlin g information * msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. 8. revision history model linearity temperature conversion time throughput package CS5566-ISZ 0.0005% -40 to +85 c 200 s 5 ksps 24-pin ssop model number peak reflow temp msl rating* max floor life CS5566-ISZ 260 c 3 7 days revision date changes pp1 mar 2008 preliminary release. contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice "preliminary" product information describes products that are in production, but for which full characterization data is not ye t available. cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information be ing relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this informatio n as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve po tential risks of deat h, personal injury, or severe prop- erty or environmental damage ("critical applications"). cirrus products are not de signed, authorized or warranted for use in products surgically implanted into the body, automotive safety or sec urity devices, life support products or other crit- ical applications. inclusion of cirrus prod ucts in such applications is understood to be fully at the customer's risk and cir- rus disclaims and makes no warra nty, express, statutory or impl ied, including the implied wa rranties of merchantability and fitness for particular purpose, with rega rd to any cirrus product that is used in such a manner. if the customer or custom- er's customer uses or permits the use of cirrus products in critical applications , customer agre es, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including at- torneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trade marks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

▲Up To Search▲

Price & Availability of CS5566-ISZ

	To Download CS5566-ISZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .